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24LCS21A
2.0 FUNCTIONAL DESCRIPTION
The 24LCS21A is designed to comply to the DDC
Standard proposed by VESA ? (Figure 3-3) with the
exception that it is not Access.bus? capable. It oper-
ates in two modes, the Transmit-Only mode and the
Bidirectional mode. There is a separate 2-wire protocol
to support each mode, each having a separate clock
input but sharing a common data line (SDA). The
device enters the Transmit-Only mode upon power-up.
In this mode, the device transmits data bits on the SDA
pin in response to a clock signal on the VCLK pin. The
device will remain in this mode until a valid high-to-low
transition is placed on the SCL input. When a valid
transition on SCL is recognized, the device will switch
into the Bidirectional mode and look for its control byte
it be initialized prior to valid data being sent in the
Transmit-Only mode ( Section 2.2 “Initialization Pro-
cedure” ). In this mode, data is transmitted on the SDA
pin in 8-bit bytes, with each byte followed by a ninth,
null bit (Figure 2-1). The clock source for the Transmit-
Only mode is provided on the VCLK pin, and a data bit
is output on the rising edge on this pin. The eight bits in
each byte are transmitted Most Significant bit first.
Each byte within the memory array will be output in
sequence. After address 7Fh in the memory array is
transmitted, the internal Address Pointers will wrap
around to the first memory location (00h) and continue.
The Bidirectional mode Clock (SCL) pin must be held
high for the device to remain in the Transmit-Only
mode.
to be sent by the master. If it detects its control byte, it
will stay in the Bidirectional mode. Otherwise, it will
2.2
Initialization Procedure
revert to the Transmit-Only mode after it sees 128
VCLK pulses.
2.1 Transmit-Only Mode
The device will power up in the Transmit-Only mode at
address 00h. This mode supports a unidirectional
2-wire protocol for continuous transmission of the
contents of the memory array. This device requires that
After V CC has stabilized, the device will be in the Trans-
mit-Only mode. Nine clock cycles on the VCLK pin
must be given to the device for it to perform internal
sychronization. During this period, the SDA pin will be
in a high-impedance state. On the rising edge of the
tenth clock cycle, the device will output the first valid
data bit which will be the Most Significant bit in address
00h. (Figure 2-2).
FIGURE 2-1:
SCL
TRANSMIT-ONLY MODE
SDA
T VAA
T VAA
Null Bit
VCLK
FIGURE 2-2:
V CC
SCL
Bit 1 (LSB)
T VHIGH T VLOW
DEVICE INITIALIZATION
Bit 1 (MSB)
T VAA
Bit 7
T VAA
SDA
High-Impedance for 9 Clock Cycles
Bit 8
Bi t 7
T VPU
VCLK
1
2
8
9
10
11
DS21161H-page 4
? 2007 Microchip Technology Inc.
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